1. Field of the Invention
The present invention relates to data processing systems and more particularly to data processing systems wherein a plurality of devices are coupled by means of a common bus to a memory and directly access the memory by way of the bus.
2. Description of the Prior Art
Many prior art computer systems have architectures in which a plurality of devices and memory are connected to a common system bus and in which each of the devices is able to directly access memory via the bus. Typically, one of the devices is a CPU which executes programs stored in memory and in response to the programs, performs arithmetic and logical operations on data stored in memory and moves data from one memory location to another. Other of the devices are I/O processors. Each I/O processor has one or more I/O devices such as terminals or disk drives attached to it and transfers data between the I/O devices and memory in response to I/O commands from the CPU. An example of such a computer system is the VS 65 built by Wang Laboratories, Inc.
In recent years, the price of memory has dropped dramatically. As a consequence, even low cost systems may have large memories. However, a large memory requires a large number of bits to address it, and consequently, the increase in memory size has been accompanied by an increase in the size of addresses. In computer systems having architectures like the one described above, an increase in memory size has required that the system designer choose between two unattractive alternatives: reimplementing all of the devices connected to the system bus so that they can generate the larger addresses or limiting devices which generate smaller addresses to those portions of memory which are addressable by means of such addresses. The invention described in the present application solves the above problem and makes it possible for devices which generate smaller addresses to access the entire memory.